1. NCCU Academic Hub
  2. Publications
  3. College of Commerce
  4. Theses
  5. Item

Publications-Theses

Article View/Open

Publication Export

Google ScholarTM

NCCU Library

Citation Infomation

Related Publications in TAIR

題名 協同設計創新對於半導體價值鏈之影響 - 以 DFM 為例
Impact of Design Collaboration Innovation for Semiconductor Value Chain: Take DFM (Design for Manufacturing) as Case
作者 申雲勇
Shen, Yun-Yong
貢獻者 溫肇東
Wen, Chao-Tung
申雲勇
Shen, Yun-Yong
關鍵詞 協同設計
創新
半導體價值鏈
奈米積體電路
微影技術
Design Collaboration
Innovation
Semiconductor Value Chain
DFM
Design for Manufacturing
lithography
日期 2005
上傳時間 12-Sep-2009 12:26:21 (UTC+8)
摘要 隨著奈米積體電路時代的來臨, 在微影技術,半導體製造技術和電路設計技術的進步已導致新的機會來整合大部份在系統中被使用到的電子功能。例如經過SoC技術提供的單晶片解決方案 - 由可重複使用的矽智財共同構成的單晶片系統 (舉例來說: 微處理器矽智財、數位信號處理矽智財、記憶體矽智財和其他的明星矽智財共同構成的單晶片系統) 可以和其他的整合系統溝通。這種包括多項技術的整合方式漸漸增加DFM 的要求, 進而創造在半導體價值鏈之中新虛擬的整合鏈模式。
     對於先進產品發展, 經由現存的分解方式價值鏈﹐從每個單一鏈節 （無晶圓設計，矽智財，電路設計自動化, 設計服務，光罩製造，晶圓製造和封裝／測試）所創造的聯合價值無法在短時間超越IDM (舉例來說: 無法提供較早的上市時間)。因此針對先進產品突破性的發展,整合每個單一鏈節變成重要的主題。本研究針對這一個整合議題提供一個新的設計合作平台作為解決方案。
     研究將以 DFM議題在半導體價值鏈中的影響作為分析。針對公司和公司間的溝通界面, 設計合作平台將會提供更多的併進價值鏈知識整合。
Advances in lithography, semiconductor processes and circuit design techniques at the nanometer IC era have led to new opportunities to integrate most of the electronic functions encountered in systems. The single-chip solution through System on Chip (SoC) which comprises reusable Silicon IP (SIP) such as Microprocessor, Digital Signal Processing (DSP), Memory and other Star SIPs enabling the system to communicate with other systems. This multidisciplinary approach calls for increasing Design for Manufacturing (DFM) needs among semiconductor value chain to enable a whole new virtual integrated chain.
     Through the existing disintegrated value chain, the synergized value contributed from each single node (fabless, SIP provider, EDA, design service, mask foundry, wafer foundry and assembly/test) could not fulfill the time-to-market benefit as the IDM provides for advanced product development. To integrate each single chain node becomes
     the important topic for advanced product breakthrough. A new design collaboration platform is proposed to address this integration issue.
     Study was conducted among this semiconductor value chain for the DFM (Design for Manufacturing) issue. The design collaboration platform addresses the inter-firm communication interface among the value chain to provide more concurrent value chain knowledge integration.
     By applying Fine’s double helix model with the evidence from DFM case, I successfully predict the re-integration trend of semiconductor industry post the disintegration model.
"Table of Contents
     ENGLISH ABSTRACT.....................................................................................................2
     CHINESE ABSTRACT.....................................................................................................5
     TABLE OF CONTENTS..................................................................................................7
     TABLE OF FIGURE AND TABLE.................................................................................9
     CHAPTER 1: INTRODUCTION...................................................................................10
     1.1 SEMICONDUCTOR IC DESIGN TREND..........................................................................10
     1.2 EVOLUTION OF THE SEMICONDUCTOR INDUSTRY VALUE CHAIN.............................11
     1.3 ISSUE OF NANOMETER IC DESIGN – MAINLY THE LITHOGRAPHY ISSUE..................14
     1.4 ISSUE OF SEMICONDUCTOR VALUE CHAIN.................................................................16
     1.5 ISSUE OF THE DESIGN PRODUCTIVITY GAP.................................................................17
     1.6 OBJECTIVE OF THIS STUDY.........................................................................................18
     1.7 METHODOLOGY OF THIS STUDY.................................................................................20
     CHAPTER 2: EVOLUTION & BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY.......................................................................................................................21
     2.1 SEMICONDUCTOR INDUSTRY EVOLUTION...................................................................21
     2.1.1 Phase 1: Fully Integrated Design and Manufacture...........................................22
     2.1.2 Phase 2: Design and Manufacture Separate: Fabless & Foundry......................22
     2.1.3 Phase 3: Design and Intellectual Property (IP) Separate: Chipless...................23
     2.2 BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY....................................................23
     2.2.1 Integrated Device Manufacturer (IDM)..............................................................24
     2.2.2 Fablite..................................................................................................................26
     2.2.3 Fabless.................................................................................................................26
     2.2.4 Intellectual Property Provider.............................................................................29
     2.2.5 Service: Design & Manufacturing.......................................................................32
     2.3 SEMICONDUCTOR VALUE CHAIN RELATIONSHIP.......................................................33
     CHAPTER 3: ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.....................35
     3.1 STATIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.............................................35
     3.2 FORCES INFLUENCING THE SEMICONDUCTOR VALUE CHAIN....................................38
     3.2.1 Threat of New Entrants........................................................................................38
     3.2.2 Power of Suppliers...............................................................................................40
     3.2.3 Power of Buyers...................................................................................................41
     3.2.4 Availability of Substitutes....................................................................................42
     3.2.5 Competitive Rivalry.............................................................................................42
     3.2.6 Five-force Analysis of Semiconductor Value Chain............................................43
     3.3 DYNAMIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.........................................44
     3.3.1 Structure in Semiconductor Markets by Competitive Intensity Quadrant Framework...........................................................................................................................45
     3.3.2 Architecture and Innovation in Semiconductor Markets......................................48
     3.3.3 Clockspeed in Semiconductor Markets.................................................................51
     3.4 DISTURBANCES THROUGHOUT THE SEMICONDUCTOR VALUE CHAIN.......................53
     3.5 BREAKING DOWN SEMICONDUCTOR VALUE CHAIN DYNAMICS................................58
     3.5.1 Internal Clockspeed.............................................................................................58
     3.5.2 External Clockspeed............................................................................................58
     3.5.3 Collaborative Value Chain Development............................................................59
     CHAPTER 4: DESIGN COLLABORATION..............................................................61
     4.1 ORGANIZATION PROXIMITY FOR PRODUCT DEVELOPMENT......................................61
     4.2 AGE OF COLLOCATION INNOVATION..........................................................................62
     4.3 AGE OF COLLABORATIVE INNOVATION......................................................................64
     4.3.1 Organizing and Managing a Co-Wired Team......................................................65
     4.3.2 Co-Wired Team Case – HP Taps Co-Wired Team for DeskJet Printer Development........................................................................................................................67
     4.4 DESIGN COLLABORATION PLATFORM........................................................................69
     4.5 DESIGN COLLABORATION SCENARIO FOR SEMICONDUCTOR INDUSTRY...................70
     4.5.1 Collaboration between Fabless and Foundy.......................................................71
     4.5.2 Collaboration among EDA, Fabless and Foundry..............................................74
     CHAPTER 5: DFM (DESIGN FOR MANUFACTURING) AS THE CASE............76
     5.1 DFM EVOLUTION.........................................................................................................76
     5.2 ADDRESSING YIELD IN DESIGN....................................................................................79
     5.3 SOPHISTICATED DESIGN RULE SETS...........................................................................80
     5.4 COLLABORATION BETWEEN FOUNDRY AND EDA – RESOLUTION ENHANCEMENT TECHNOLOGY (RET).....................................................................................82
     5.5 COLLABORATION AMONG FABLESS, FOUNDRY AND EDA..........................................84
     5.6 FEED-FORWARD COLLABORATION FROM FABLESS TO FOUNDRY – DESIGN-ENABLED LITHOGRAPHY..........................................................................................................87
     5.7 FEEDBACK COLLABORATION FROM FOUNDRY TO FABLESS – LITHOGRAPHY-ENABLED DESIGN......................................................................................................................89
     5.8 DESIGN COLLABORATION AS THE INNOVATION PLATFORM TO CROSS THE VALUE CHAIN FOR DFM.........................................................................................................91
     5.9 Technological Innovation.........................................................................................93
     5.9.2 Competitive Intensity............................................................................................94
     5.10 Collaborative Value Chain Development.................................................................95
     5.11 CASE OF DESIGN COLLABORATION PLATFORM – DFM DESIGN SUPPORT ECOSYSTEM BY TSMC...........................................................................................................100
     CHAPTER 6: CONCLUSION AND IMPLICATIONS.............................................106
     6.1 APPLY DOUBLE HELIX MODEL TO PREDICT THE VALUE CHAIN TREND....................106
     6.2 PROVIDE DESIGN COLLABORATION PLATFORM TO FACILITATE THE NANOMETER DESIGN TRANSITION..........................................................................................107
     6.3 IMPLICATION FOR MANAGING SUCCESSFUL DFM....................................................108
     REFERENCES...............................................................................................................110
     Table of Figure and Table
     FIGURE 1-1: SOC DESIGN..................................................................................................11
     FIGURE 1-2: DISINTEGRATION OF SEMICONDUCTOR VALUE CHAIN...................................13
     FIGURE 1-3: SUBWAVELENGTH ISSUE................................................................................15
     FIGURE 1-4: MASK MANUFACTURING...............................................................................16
     FIGURE 1-5: PATTERN IS LOST FOR ADVANCED TECHNOLOGY...........................................16
     FIGURE 1-6: MASK MANUFACTURING BETWEEN STAFF MONTH VS. LOGIC TRANSISTORS GROWTH (SOURCE : SEMATECH)...............................................................................18
     FIGURE 1-7: EVOLUTION OF SEMICONDUCTOR VALUE-CHAIN..........................................19
     FIGURE 2-1: SEMICONDUCTOR COMPANY ECOLOGY.........................................................21
     TABLE 2-1: 2005 WORLDWIDE TOP 50 SEMICONDUCTOR..................................................25
     TABLE 2-2: 2005 TOP 40 FABLESS IC SUPPLIERS..............................................................28
     TABLE 2-3: 2004 TOP 10 SEMICONDUCTOR IP VENDOR....................................................30
     TABLE 2-4: 2004 WORLDWIDE TOP 35 FABLESS IC SUPPLIER...........................................31
     FIGURE 2-2: SEMICONDUCTOR VALUE CHAIN RELATIONSHIP...........................................34
     FIGURE 3-1: PORTER’S 5-FORCES MODEL..........................................................................36
     TABLE 3-1: TOP 8 IC PRODUCT TYPE IN 2005....................................................................38
     FIGURE 3-2: FIVE-FORCE ANALYSIS OF SEMICONDUCTOR VALUE CHAIN..........................43
     FIGURE 3-3: DOUBLE HELIX OF INDUSTRY CYCLING.........................................................53
     FIGURE 3-4: SEMICONDUCTOR INDUSTRY VALUE CHAIN..................................................54
     FIGURE 3-5: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS...................57
     FIGURE 4-1: INTERACTION ACTIVITIES BETWEEN FOUNDRY AND FABLESS.........................72
     FIGURE 4-2: INTERACTION ACTIVITIES AMONG FABLES, IP/LIBRARY PROVIDER, MASK HOUSE, FOUNDRY, ASSEMBLY HOUSE, TESTING HOUSE AND CUSTOMER.....................72
     FIGURE 5-1: AT NANOMETER NODES, DESIGNERS FACE PHYSICAL AND ELECTRICAL EFFECTS THAT SIGNIFICANTLY INCREASE THE LIKELIHOOD OF SILICON FAILURES WITH CONVENTIONAL DEVELOPMENT METHODOLOGIES.....................................................77
     FIGURE 5-2: AT NANOMETER NODES, PERFORMANCE AND LITHOGRAPHY EFFECTS BECOME KEY INFLUENCERS OF YIELD, REQUIRING MORE COMPREHENSIVE YIELD-ENHANCEMENT APPROACHES.....................................................................................79
     FIGURE 5-3: ITRS 2003 ROADMAP SCENARIO....................................................................83
     FIGURE 5-4: DESIGN-AWARE PROCESSING PROMISES TO LIMIT INCREASINGLY LONG RET RUN TIMES AND HELP OPTIMIZE KEY DESIGN STRUCTURES.........................................88
     FIGURE 5-5: A FULLY INTEGRATED PRE-TAPEOUT DESIGN FLOW MINIMIZES COSTLY RE-DESIGNS AND MASKS LOST TO ERRONEOUS DATA.......................................................90
     FIGURE 5-6: COLLABORATION AMONG FABLES, EDA VENDOR AND FOUNDRY..................92
     FIGURE 5-7: MANUFACTURING KNOWLEDGE MOVEMENT ALONG THE VALUE CHAIN.........93
     FIGURE 5-8: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS CONSIDERING DFM..........................................................................................................................96
     FIGURE 5-9: TSMC.COM PORTAL....................................................................................101
     FIGURE 5-10: TSMC ONLINE PORTAL.............................................................................102
     FIGURE 5-11: TSMC DFM-COMPLIANCE INITIATIVE......................................................103
參考文獻 1. Chang, Jonathan Yung-Cheng & Cheng, Fan-Tien (2005), “Framework Development of an Engineering-Chain-Management-System for the Semiconductor Industry”, 3rd IEEE International Conference on Industrial Informatics, 2005.
2. Chiang, Shang-yi (2001), “Foundries and the Dawn of an Open IP Era”, IEEE Computer, April 2001, pp. 43-46
3. Daetz, D. (1987), “The Effect of Product Design on Product Quality and Product Cost,” Quality Progress, Jun. 1987, pp. 40-44
4. Edelstone, Mark (2003), “Are IDMs Obsolete?”, Morgan Stanley Presentation, October 8, 2003
5. Fabrycky, W. J. (1985), “System Life-Cycle Engineering: Bringing Competitive Products into Being”, Workshop on Opportunities for Engineering Research, Focused on Emerging Engineering Systems, Washington, D. C., July 15, 1985.
6. Fabrycky, W. J. (1987), “Designing for the Life-cycle,” Mechanical Engineering, Jan, 1987, pp. 72-74.
7. Fine, Charles H (1998), Clockspeed – Winning Industry Control in the Age of Temporary advantage, Preseus Books.
8. Kirkland, C. (1988), “Meet Two Architects of Design-Integrated
Manufacturing,” Plastics World, Dec. 1988, pp. 46-50.
9. SEMATECH (1995), Personal Communication from Dick Bushroe.
10. Staud, Wolf & Chen, Fung & Hsu, Stephen & Broeke, Doug van den (2005). “Subwavelength Imaging at k1<0.3”. Semiconductor International. Santa Clara, Calif. USA.
11. Stoll, H. W. (1988), “Design for Manufacture,” Tools and Manufacturing Engineers Handbook: Manufacturing Management, vol. 5, 1988, pp. 13-1-13-32.
12. Stoll, H. W. (1988), “Design for Manufacturing,” Manufacturing
Engineering, Jan. 1988, pp. 67-73.
13. Stoll, H. W. (1988),”Design for Manufacture,” Tool and Manufacturing Engineers Handbook, vol. 5, SME Press, 1988, pp. 13-1-13-32.
14. Stoll, H. W. (1990), “Design for Manufacturing,” Simultaneous Engineering, C. W. Allen ed., SME Press, 1990, pp. 23-29.
15. Su, Yea-Huey & Guo, Ruey-Shan & Chang, Shi-Chung (2004), "Inter-firm Collaboration Mechanism in Process Development and Product Design between Foundry and Fabless Design House" Proceedings of the 2004 IEEE Semiconductor Manufacturing Technology Workshop (SMTW 2004), pp. 47-50, Hsinchu Taiwan, September 9-10, 2004.
16. Utterback, James (1996). Mastering the Dynamics of Innovation, Harvard Business School Press, 1996.
描述 碩士
國立政治大學
經營管理碩士學程(EMBA)
92932923
94
資料來源 http://thesis.lib.nccu.edu.tw/record/#G0092932923
資料類型 thesis
dc.contributor.advisor 溫肇東zh_TW
dc.contributor.advisor Wen, Chao-Tungen_US
dc.contributor.author (Authors) 申雲勇zh_TW
dc.contributor.author (Authors) Shen, Yun-Yongen_US
dc.creator (作者) 申雲勇zh_TW
dc.creator (作者) Shen, Yun-Yongen_US
dc.date (日期) 2005en_US
dc.date.accessioned 12-Sep-2009 12:26:21 (UTC+8)-
dc.date.available 12-Sep-2009 12:26:21 (UTC+8)-
dc.date.issued (上傳時間) 12-Sep-2009 12:26:21 (UTC+8)-
dc.identifier (Other Identifiers) G0092932923en_US
dc.identifier.uri (URI) https://nccur.lib.nccu.edu.tw/handle/140.119/30576-
dc.description (描述) 碩士zh_TW
dc.description (描述) 國立政治大學zh_TW
dc.description (描述) 經營管理碩士學程(EMBA)zh_TW
dc.description (描述) 92932923zh_TW
dc.description (描述) 94zh_TW
dc.description.abstract (摘要) 隨著奈米積體電路時代的來臨, 在微影技術,半導體製造技術和電路設計技術的進步已導致新的機會來整合大部份在系統中被使用到的電子功能。例如經過SoC技術提供的單晶片解決方案 - 由可重複使用的矽智財共同構成的單晶片系統 (舉例來說: 微處理器矽智財、數位信號處理矽智財、記憶體矽智財和其他的明星矽智財共同構成的單晶片系統) 可以和其他的整合系統溝通。這種包括多項技術的整合方式漸漸增加DFM 的要求, 進而創造在半導體價值鏈之中新虛擬的整合鏈模式。
     對於先進產品發展, 經由現存的分解方式價值鏈﹐從每個單一鏈節 （無晶圓設計，矽智財，電路設計自動化, 設計服務，光罩製造，晶圓製造和封裝／測試）所創造的聯合價值無法在短時間超越IDM (舉例來說: 無法提供較早的上市時間)。因此針對先進產品突破性的發展,整合每個單一鏈節變成重要的主題。本研究針對這一個整合議題提供一個新的設計合作平台作為解決方案。
     研究將以 DFM議題在半導體價值鏈中的影響作為分析。針對公司和公司間的溝通界面, 設計合作平台將會提供更多的併進價值鏈知識整合。		zh_TW
dc.description.abstract (摘要) Advances in lithography, semiconductor processes and circuit design techniques at the nanometer IC era have led to new opportunities to integrate most of the electronic functions encountered in systems. The single-chip solution through System on Chip (SoC) which comprises reusable Silicon IP (SIP) such as Microprocessor, Digital Signal Processing (DSP), Memory and other Star SIPs enabling the system to communicate with other systems. This multidisciplinary approach calls for increasing Design for Manufacturing (DFM) needs among semiconductor value chain to enable a whole new virtual integrated chain.
     Through the existing disintegrated value chain, the synergized value contributed from each single node (fabless, SIP provider, EDA, design service, mask foundry, wafer foundry and assembly/test) could not fulfill the time-to-market benefit as the IDM provides for advanced product development. To integrate each single chain node becomes
     the important topic for advanced product breakthrough. A new design collaboration platform is proposed to address this integration issue.
     Study was conducted among this semiconductor value chain for the DFM (Design for Manufacturing) issue. The design collaboration platform addresses the inter-firm communication interface among the value chain to provide more concurrent value chain knowledge integration.
     By applying Fine’s double helix model with the evidence from DFM case, I successfully predict the re-integration trend of semiconductor industry post the disintegration model.		en_US
dc.description.abstract (摘要) "Table of Contents
     ENGLISH ABSTRACT.....................................................................................................2
     CHINESE ABSTRACT.....................................................................................................5
     TABLE OF CONTENTS..................................................................................................7
     TABLE OF FIGURE AND TABLE.................................................................................9
     CHAPTER 1: INTRODUCTION...................................................................................10
     1.1 SEMICONDUCTOR IC DESIGN TREND..........................................................................10
     1.2 EVOLUTION OF THE SEMICONDUCTOR INDUSTRY VALUE CHAIN.............................11
     1.3 ISSUE OF NANOMETER IC DESIGN – MAINLY THE LITHOGRAPHY ISSUE..................14
     1.4 ISSUE OF SEMICONDUCTOR VALUE CHAIN.................................................................16
     1.5 ISSUE OF THE DESIGN PRODUCTIVITY GAP.................................................................17
     1.6 OBJECTIVE OF THIS STUDY.........................................................................................18
     1.7 METHODOLOGY OF THIS STUDY.................................................................................20
     CHAPTER 2: EVOLUTION & BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY.......................................................................................................................21
     2.1 SEMICONDUCTOR INDUSTRY EVOLUTION...................................................................21
     2.1.1 Phase 1: Fully Integrated Design and Manufacture...........................................22
     2.1.2 Phase 2: Design and Manufacture Separate: Fabless & Foundry......................22
     2.1.3 Phase 3: Design and Intellectual Property (IP) Separate: Chipless...................23
     2.2 BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY....................................................23
     2.2.1 Integrated Device Manufacturer (IDM)..............................................................24
     2.2.2 Fablite..................................................................................................................26
     2.2.3 Fabless.................................................................................................................26
     2.2.4 Intellectual Property Provider.............................................................................29
     2.2.5 Service: Design & Manufacturing.......................................................................32
     2.3 SEMICONDUCTOR VALUE CHAIN RELATIONSHIP.......................................................33
     CHAPTER 3: ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.....................35
     3.1 STATIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.............................................35
     3.2 FORCES INFLUENCING THE SEMICONDUCTOR VALUE CHAIN....................................38
     3.2.1 Threat of New Entrants........................................................................................38
     3.2.2 Power of Suppliers...............................................................................................40
     3.2.3 Power of Buyers...................................................................................................41
     3.2.4 Availability of Substitutes....................................................................................42
     3.2.5 Competitive Rivalry.............................................................................................42
     3.2.6 Five-force Analysis of Semiconductor Value Chain............................................43
     3.3 DYNAMIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.........................................44
     3.3.1 Structure in Semiconductor Markets by Competitive Intensity Quadrant Framework...........................................................................................................................45
     3.3.2 Architecture and Innovation in Semiconductor Markets......................................48
     3.3.3 Clockspeed in Semiconductor Markets.................................................................51
     3.4 DISTURBANCES THROUGHOUT THE SEMICONDUCTOR VALUE CHAIN.......................53
     3.5 BREAKING DOWN SEMICONDUCTOR VALUE CHAIN DYNAMICS................................58
     3.5.1 Internal Clockspeed.............................................................................................58
     3.5.2 External Clockspeed............................................................................................58
     3.5.3 Collaborative Value Chain Development............................................................59
     CHAPTER 4: DESIGN COLLABORATION..............................................................61
     4.1 ORGANIZATION PROXIMITY FOR PRODUCT DEVELOPMENT......................................61
     4.2 AGE OF COLLOCATION INNOVATION..........................................................................62
     4.3 AGE OF COLLABORATIVE INNOVATION......................................................................64
     4.3.1 Organizing and Managing a Co-Wired Team......................................................65
     4.3.2 Co-Wired Team Case – HP Taps Co-Wired Team for DeskJet Printer Development........................................................................................................................67
     4.4 DESIGN COLLABORATION PLATFORM........................................................................69
     4.5 DESIGN COLLABORATION SCENARIO FOR SEMICONDUCTOR INDUSTRY...................70
     4.5.1 Collaboration between Fabless and Foundy.......................................................71
     4.5.2 Collaboration among EDA, Fabless and Foundry..............................................74
     CHAPTER 5: DFM (DESIGN FOR MANUFACTURING) AS THE CASE............76
     5.1 DFM EVOLUTION.........................................................................................................76
     5.2 ADDRESSING YIELD IN DESIGN....................................................................................79
     5.3 SOPHISTICATED DESIGN RULE SETS...........................................................................80
     5.4 COLLABORATION BETWEEN FOUNDRY AND EDA – RESOLUTION ENHANCEMENT TECHNOLOGY (RET).....................................................................................82
     5.5 COLLABORATION AMONG FABLESS, FOUNDRY AND EDA..........................................84
     5.6 FEED-FORWARD COLLABORATION FROM FABLESS TO FOUNDRY – DESIGN-ENABLED LITHOGRAPHY..........................................................................................................87
     5.7 FEEDBACK COLLABORATION FROM FOUNDRY TO FABLESS – LITHOGRAPHY-ENABLED DESIGN......................................................................................................................89
     5.8 DESIGN COLLABORATION AS THE INNOVATION PLATFORM TO CROSS THE VALUE CHAIN FOR DFM.........................................................................................................91
     5.9 Technological Innovation.........................................................................................93
     5.9.2 Competitive Intensity............................................................................................94
     5.10 Collaborative Value Chain Development.................................................................95
     5.11 CASE OF DESIGN COLLABORATION PLATFORM – DFM DESIGN SUPPORT ECOSYSTEM BY TSMC...........................................................................................................100
     CHAPTER 6: CONCLUSION AND IMPLICATIONS.............................................106
     6.1 APPLY DOUBLE HELIX MODEL TO PREDICT THE VALUE CHAIN TREND....................106
     6.2 PROVIDE DESIGN COLLABORATION PLATFORM TO FACILITATE THE NANOMETER DESIGN TRANSITION..........................................................................................107
     6.3 IMPLICATION FOR MANAGING SUCCESSFUL DFM....................................................108
     REFERENCES...............................................................................................................110
     Table of Figure and Table
     FIGURE 1-1: SOC DESIGN..................................................................................................11
     FIGURE 1-2: DISINTEGRATION OF SEMICONDUCTOR VALUE CHAIN...................................13
     FIGURE 1-3: SUBWAVELENGTH ISSUE................................................................................15
     FIGURE 1-4: MASK MANUFACTURING...............................................................................16
     FIGURE 1-5: PATTERN IS LOST FOR ADVANCED TECHNOLOGY...........................................16
     FIGURE 1-6: MASK MANUFACTURING BETWEEN STAFF MONTH VS. LOGIC TRANSISTORS GROWTH (SOURCE : SEMATECH)...............................................................................18
     FIGURE 1-7: EVOLUTION OF SEMICONDUCTOR VALUE-CHAIN..........................................19
     FIGURE 2-1: SEMICONDUCTOR COMPANY ECOLOGY.........................................................21
     TABLE 2-1: 2005 WORLDWIDE TOP 50 SEMICONDUCTOR..................................................25
     TABLE 2-2: 2005 TOP 40 FABLESS IC SUPPLIERS..............................................................28
     TABLE 2-3: 2004 TOP 10 SEMICONDUCTOR IP VENDOR....................................................30
     TABLE 2-4: 2004 WORLDWIDE TOP 35 FABLESS IC SUPPLIER...........................................31
     FIGURE 2-2: SEMICONDUCTOR VALUE CHAIN RELATIONSHIP...........................................34
     FIGURE 3-1: PORTER’S 5-FORCES MODEL..........................................................................36
     TABLE 3-1: TOP 8 IC PRODUCT TYPE IN 2005....................................................................38
     FIGURE 3-2: FIVE-FORCE ANALYSIS OF SEMICONDUCTOR VALUE CHAIN..........................43
     FIGURE 3-3: DOUBLE HELIX OF INDUSTRY CYCLING.........................................................53
     FIGURE 3-4: SEMICONDUCTOR INDUSTRY VALUE CHAIN..................................................54
     FIGURE 3-5: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS...................57
     FIGURE 4-1: INTERACTION ACTIVITIES BETWEEN FOUNDRY AND FABLESS.........................72
     FIGURE 4-2: INTERACTION ACTIVITIES AMONG FABLES, IP/LIBRARY PROVIDER, MASK HOUSE, FOUNDRY, ASSEMBLY HOUSE, TESTING HOUSE AND CUSTOMER.....................72
     FIGURE 5-1: AT NANOMETER NODES, DESIGNERS FACE PHYSICAL AND ELECTRICAL EFFECTS THAT SIGNIFICANTLY INCREASE THE LIKELIHOOD OF SILICON FAILURES WITH CONVENTIONAL DEVELOPMENT METHODOLOGIES.....................................................77
     FIGURE 5-2: AT NANOMETER NODES, PERFORMANCE AND LITHOGRAPHY EFFECTS BECOME KEY INFLUENCERS OF YIELD, REQUIRING MORE COMPREHENSIVE YIELD-ENHANCEMENT APPROACHES.....................................................................................79
     FIGURE 5-3: ITRS 2003 ROADMAP SCENARIO....................................................................83
     FIGURE 5-4: DESIGN-AWARE PROCESSING PROMISES TO LIMIT INCREASINGLY LONG RET RUN TIMES AND HELP OPTIMIZE KEY DESIGN STRUCTURES.........................................88
     FIGURE 5-5: A FULLY INTEGRATED PRE-TAPEOUT DESIGN FLOW MINIMIZES COSTLY RE-DESIGNS AND MASKS LOST TO ERRONEOUS DATA.......................................................90
     FIGURE 5-6: COLLABORATION AMONG FABLES, EDA VENDOR AND FOUNDRY..................92
     FIGURE 5-7: MANUFACTURING KNOWLEDGE MOVEMENT ALONG THE VALUE CHAIN.........93
     FIGURE 5-8: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS CONSIDERING DFM..........................................................................................................................96
     FIGURE 5-9: TSMC.COM PORTAL....................................................................................101
     FIGURE 5-10: TSMC ONLINE PORTAL.............................................................................102
     FIGURE 5-11: TSMC DFM-COMPLIANCE INITIATIVE......................................................103		-
dc.description.tableofcontents Table of Contents
     ENGLISH ABSTRACT.....................................................................................................2
     CHINESE ABSTRACT.....................................................................................................5
     TABLE OF CONTENTS..................................................................................................7
     TABLE OF FIGURE AND TABLE.................................................................................9
     CHAPTER 1: INTRODUCTION...................................................................................10
     1.1 SEMICONDUCTOR IC DESIGN TREND..........................................................................10
     1.2 EVOLUTION OF THE SEMICONDUCTOR INDUSTRY VALUE CHAIN.............................11
     1.3 ISSUE OF NANOMETER IC DESIGN – MAINLY THE LITHOGRAPHY ISSUE..................14
     1.4 ISSUE OF SEMICONDUCTOR VALUE CHAIN.................................................................16
     1.5 ISSUE OF THE DESIGN PRODUCTIVITY GAP.................................................................17
     1.6 OBJECTIVE OF THIS STUDY.........................................................................................18
     1.7 METHODOLOGY OF THIS STUDY.................................................................................20
     CHAPTER 2: EVOLUTION & BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY.......................................................................................................................21
     2.1 SEMICONDUCTOR INDUSTRY EVOLUTION...................................................................21
     2.1.1 Phase 1: Fully Integrated Design and Manufacture...........................................22
     2.1.2 Phase 2: Design and Manufacture Separate: Fabless & Foundry......................22
     2.1.3 Phase 3: Design and Intellectual Property (IP) Separate: Chipless...................23
     2.2 BUSINESS MODEL OF SEMICONDUCTOR INDUSTRY....................................................23
     2.2.1 Integrated Device Manufacturer (IDM)..............................................................24
     2.2.2 Fablite..................................................................................................................26
     2.2.3 Fabless.................................................................................................................26
     2.2.4 Intellectual Property Provider.............................................................................29
     2.2.5 Service: Design & Manufacturing.......................................................................32
     2.3 SEMICONDUCTOR VALUE CHAIN RELATIONSHIP.......................................................33
     CHAPTER 3: ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.....................35
     3.1 STATIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.............................................35
     3.2 FORCES INFLUENCING THE SEMICONDUCTOR VALUE CHAIN....................................38
     3.2.1 Threat of New Entrants........................................................................................38
     3.2.2 Power of Suppliers...............................................................................................40
     3.2.3 Power of Buyers...................................................................................................41
     3.2.4 Availability of Substitutes....................................................................................42
     3.2.5 Competitive Rivalry.............................................................................................42
     3.2.6 Five-force Analysis of Semiconductor Value Chain............................................43
     3.3 DYNAMIC ANALYSIS OF SEMICONDUCTOR VALUE CHAIN.........................................44
     3.3.1 Structure in Semiconductor Markets by Competitive Intensity Quadrant Framework...........................................................................................................................45
     3.3.2 Architecture and Innovation in Semiconductor Markets......................................48
     3.3.3 Clockspeed in Semiconductor Markets.................................................................51
     3.4 DISTURBANCES THROUGHOUT THE SEMICONDUCTOR VALUE CHAIN.......................53
     3.5 BREAKING DOWN SEMICONDUCTOR VALUE CHAIN DYNAMICS................................58
     3.5.1 Internal Clockspeed.............................................................................................58
     3.5.2 External Clockspeed............................................................................................58
     3.5.3 Collaborative Value Chain Development............................................................59
     CHAPTER 4: DESIGN COLLABORATION..............................................................61
     4.1 ORGANIZATION PROXIMITY FOR PRODUCT DEVELOPMENT......................................61
     4.2 AGE OF COLLOCATION INNOVATION..........................................................................62
     4.3 AGE OF COLLABORATIVE INNOVATION......................................................................64
     4.3.1 Organizing and Managing a Co-Wired Team......................................................65
     4.3.2 Co-Wired Team Case – HP Taps Co-Wired Team for DeskJet Printer Development........................................................................................................................67
     4.4 DESIGN COLLABORATION PLATFORM........................................................................69
     4.5 DESIGN COLLABORATION SCENARIO FOR SEMICONDUCTOR INDUSTRY...................70
     4.5.1 Collaboration between Fabless and Foundy.......................................................71
     4.5.2 Collaboration among EDA, Fabless and Foundry..............................................74
     CHAPTER 5: DFM (DESIGN FOR MANUFACTURING) AS THE CASE............76
     5.1 DFM EVOLUTION.........................................................................................................76
     5.2 ADDRESSING YIELD IN DESIGN....................................................................................79
     5.3 SOPHISTICATED DESIGN RULE SETS...........................................................................80
     5.4 COLLABORATION BETWEEN FOUNDRY AND EDA – RESOLUTION ENHANCEMENT TECHNOLOGY (RET).....................................................................................82
     5.5 COLLABORATION AMONG FABLESS, FOUNDRY AND EDA..........................................84
     5.6 FEED-FORWARD COLLABORATION FROM FABLESS TO FOUNDRY – DESIGN-ENABLED LITHOGRAPHY..........................................................................................................87
     5.7 FEEDBACK COLLABORATION FROM FOUNDRY TO FABLESS – LITHOGRAPHY-ENABLED DESIGN......................................................................................................................89
     5.8 DESIGN COLLABORATION AS THE INNOVATION PLATFORM TO CROSS THE VALUE CHAIN FOR DFM.........................................................................................................91
     5.9 Technological Innovation.........................................................................................93
     5.9.2 Competitive Intensity............................................................................................94
     5.10 Collaborative Value Chain Development.................................................................95
     5.11 CASE OF DESIGN COLLABORATION PLATFORM – DFM DESIGN SUPPORT ECOSYSTEM BY TSMC...........................................................................................................100
     CHAPTER 6: CONCLUSION AND IMPLICATIONS.............................................106
     6.1 APPLY DOUBLE HELIX MODEL TO PREDICT THE VALUE CHAIN TREND....................106
     6.2 PROVIDE DESIGN COLLABORATION PLATFORM TO FACILITATE THE NANOMETER DESIGN TRANSITION..........................................................................................107
     6.3 IMPLICATION FOR MANAGING SUCCESSFUL DFM....................................................108
     REFERENCES...............................................................................................................110
     Table of Figure and Table
     FIGURE 1-1: SOC DESIGN..................................................................................................11
     FIGURE 1-2: DISINTEGRATION OF SEMICONDUCTOR VALUE CHAIN...................................13
     FIGURE 1-3: SUBWAVELENGTH ISSUE................................................................................15
     FIGURE 1-4: MASK MANUFACTURING...............................................................................16
     FIGURE 1-5: PATTERN IS LOST FOR ADVANCED TECHNOLOGY...........................................16
     FIGURE 1-6: MASK MANUFACTURING BETWEEN STAFF MONTH VS. LOGIC TRANSISTORS GROWTH (SOURCE : SEMATECH)...............................................................................18
     FIGURE 1-7: EVOLUTION OF SEMICONDUCTOR VALUE-CHAIN..........................................19
     FIGURE 2-1: SEMICONDUCTOR COMPANY ECOLOGY.........................................................21
     TABLE 2-1: 2005 WORLDWIDE TOP 50 SEMICONDUCTOR..................................................25
     TABLE 2-2: 2005 TOP 40 FABLESS IC SUPPLIERS..............................................................28
     TABLE 2-3: 2004 TOP 10 SEMICONDUCTOR IP VENDOR....................................................30
     TABLE 2-4: 2004 WORLDWIDE TOP 35 FABLESS IC SUPPLIER...........................................31
     FIGURE 2-2: SEMICONDUCTOR VALUE CHAIN RELATIONSHIP...........................................34
     FIGURE 3-1: PORTER’S 5-FORCES MODEL..........................................................................36
     TABLE 3-1: TOP 8 IC PRODUCT TYPE IN 2005....................................................................38
     FIGURE 3-2: FIVE-FORCE ANALYSIS OF SEMICONDUCTOR VALUE CHAIN..........................43
     FIGURE 3-3: DOUBLE HELIX OF INDUSTRY CYCLING.........................................................53
     FIGURE 3-4: SEMICONDUCTOR INDUSTRY VALUE CHAIN..................................................54
     FIGURE 3-5: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS...................57
     FIGURE 4-1: INTERACTION ACTIVITIES BETWEEN FOUNDRY AND FABLESS.........................72
     FIGURE 4-2: INTERACTION ACTIVITIES AMONG FABLES, IP/LIBRARY PROVIDER, MASK HOUSE, FOUNDRY, ASSEMBLY HOUSE, TESTING HOUSE AND CUSTOMER.....................72
     FIGURE 5-1: AT NANOMETER NODES, DESIGNERS FACE PHYSICAL AND ELECTRICAL EFFECTS THAT SIGNIFICANTLY INCREASE THE LIKELIHOOD OF SILICON FAILURES WITH CONVENTIONAL DEVELOPMENT METHODOLOGIES.....................................................77
     FIGURE 5-2: AT NANOMETER NODES, PERFORMANCE AND LITHOGRAPHY EFFECTS BECOME KEY INFLUENCERS OF YIELD, REQUIRING MORE COMPREHENSIVE YIELD-ENHANCEMENT APPROACHES.....................................................................................79
     FIGURE 5-3: ITRS 2003 ROADMAP SCENARIO....................................................................83
     FIGURE 5-4: DESIGN-AWARE PROCESSING PROMISES TO LIMIT INCREASINGLY LONG RET RUN TIMES AND HELP OPTIMIZE KEY DESIGN STRUCTURES.........................................88
     FIGURE 5-5: A FULLY INTEGRATED PRE-TAPEOUT DESIGN FLOW MINIMIZES COSTLY RE-DESIGNS AND MASKS LOST TO ERRONEOUS DATA.......................................................90
     FIGURE 5-6: COLLABORATION AMONG FABLES, EDA VENDOR AND FOUNDRY..................92
     FIGURE 5-7: MANUFACTURING KNOWLEDGE MOVEMENT ALONG THE VALUE CHAIN.........93
     FIGURE 5-8: DOUBLE HELIX OF SEMICONDUCTOR VALUE CHAIN DYNAMICS CONSIDERING DFM..........................................................................................................................96
     FIGURE 5-9: TSMC.COM PORTAL....................................................................................101
     FIGURE 5-10: TSMC ONLINE PORTAL.............................................................................102
     FIGURE 5-11: TSMC DFM-COMPLIANCE INITIATIVE......................................................103		zh_TW
dc.language.iso en_US-
dc.source.uri (資料來源) http://thesis.lib.nccu.edu.tw/record/#G0092932923en_US
dc.subject (關鍵詞) 協同設計zh_TW
dc.subject (關鍵詞) 創新zh_TW
dc.subject (關鍵詞) 半導體價值鏈zh_TW
dc.subject (關鍵詞) 奈米積體電路zh_TW
dc.subject (關鍵詞) 微影技術zh_TW
dc.subject (關鍵詞) Design Collaborationen_US
dc.subject (關鍵詞) Innovationen_US
dc.subject (關鍵詞) Semiconductor Value Chainen_US
dc.subject (關鍵詞) DFMen_US
dc.subject (關鍵詞) Design for Manufacturingen_US
dc.subject (關鍵詞) lithographyen_US
dc.title (題名) 協同設計創新對於半導體價值鏈之影響 - 以 DFM 為例zh_TW
dc.title (題名) Impact of Design Collaboration Innovation for Semiconductor Value Chain: Take DFM (Design for Manufacturing) as Caseen_US
dc.type (資料類型) thesisen
dc.relation.reference (參考文獻) 1. Chang, Jonathan Yung-Cheng & Cheng, Fan-Tien (2005), “Framework Development of an Engineering-Chain-Management-System for the Semiconductor Industry”, 3rd IEEE International Conference on Industrial Informatics, 2005.zh_TW
dc.relation.reference (參考文獻) 2. Chiang, Shang-yi (2001), “Foundries and the Dawn of an Open IP Era”, IEEE Computer, April 2001, pp. 43-46zh_TW
dc.relation.reference (參考文獻) 3. Daetz, D. (1987), “The Effect of Product Design on Product Quality and Product Cost,” Quality Progress, Jun. 1987, pp. 40-44zh_TW
dc.relation.reference (參考文獻) 4. Edelstone, Mark (2003), “Are IDMs Obsolete?”, Morgan Stanley Presentation, October 8, 2003zh_TW
dc.relation.reference (參考文獻) 5. Fabrycky, W. J. (1985), “System Life-Cycle Engineering: Bringing Competitive Products into Being”, Workshop on Opportunities for Engineering Research, Focused on Emerging Engineering Systems, Washington, D. C., July 15, 1985.zh_TW
dc.relation.reference (參考文獻) 6. Fabrycky, W. J. (1987), “Designing for the Life-cycle,” Mechanical Engineering, Jan, 1987, pp. 72-74.zh_TW
dc.relation.reference (參考文獻) 7. Fine, Charles H (1998), Clockspeed – Winning Industry Control in the Age of Temporary advantage, Preseus Books.zh_TW
dc.relation.reference (參考文獻) 8. Kirkland, C. (1988), “Meet Two Architects of Design-Integratedzh_TW
dc.relation.reference (參考文獻) Manufacturing,” Plastics World, Dec. 1988, pp. 46-50.zh_TW
dc.relation.reference (參考文獻) 9. SEMATECH (1995), Personal Communication from Dick Bushroe.zh_TW
dc.relation.reference (參考文獻) 10. Staud, Wolf & Chen, Fung & Hsu, Stephen & Broeke, Doug van den (2005). “Subwavelength Imaging at k1<0.3”. Semiconductor International. Santa Clara, Calif. USA.zh_TW
dc.relation.reference (參考文獻) 11. Stoll, H. W. (1988), “Design for Manufacture,” Tools and Manufacturing Engineers Handbook: Manufacturing Management, vol. 5, 1988, pp. 13-1-13-32.zh_TW
dc.relation.reference (參考文獻) 12. Stoll, H. W. (1988), “Design for Manufacturing,” Manufacturingzh_TW
dc.relation.reference (參考文獻) Engineering, Jan. 1988, pp. 67-73.zh_TW
dc.relation.reference (參考文獻) 13. Stoll, H. W. (1988),”Design for Manufacture,” Tool and Manufacturing Engineers Handbook, vol. 5, SME Press, 1988, pp. 13-1-13-32.zh_TW
dc.relation.reference (參考文獻) 14. Stoll, H. W. (1990), “Design for Manufacturing,” Simultaneous Engineering, C. W. Allen ed., SME Press, 1990, pp. 23-29.zh_TW
dc.relation.reference (參考文獻) 15. Su, Yea-Huey & Guo, Ruey-Shan & Chang, Shi-Chung (2004), "Inter-firm Collaboration Mechanism in Process Development and Product Design between Foundry and Fabless Design House" Proceedings of the 2004 IEEE Semiconductor Manufacturing Technology Workshop (SMTW 2004), pp. 47-50, Hsinchu Taiwan, September 9-10, 2004.zh_TW
dc.relation.reference (參考文獻) 16. Utterback, James (1996). Mastering the Dynamics of Innovation, Harvard Business School Press, 1996.zh_TW