| dc.contributor | 企管系 | |
| dc.creator (作者) | Kuo;Geng-Sheng;Khan, A.;Watson, P.;Le, D.;Nguyen, T.;Yang, S.;Bennett, P.;Huang, Pokai;Gill, J.;Hawkins, C.;Goodenough, J.;Wang, Demin;Ahmed, I.;Tran, P.;Mak, H.;Kim, Oanh;Martin, F.;Fan, Y.;Ge, D.;Kung, J.;Shek, V. | |
| dc.creator (作者) | 郭更生 | zh_TW |
| dc.date (日期) | 2006-08 | |
| dc.date.accessioned | 6-Mar-2015 11:09:14 (UTC+8) | - |
| dc.date.available | 6-Mar-2015 11:09:14 (UTC+8) | - |
| dc.date.issued (上傳時間) | 6-Mar-2015 11:09:14 (UTC+8) | - |
| dc.identifier.uri (URI) | http://nccur.lib.nccu.edu.tw/handle/140.119/73682 | - |
| dc.description.abstract (摘要) | An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and clock rate optimization, single-pass RTL synthesis, VDD selection, power optimization and timing and electrical closure in a multi-VDD domain design are described. A 40% reduction in dynamic and a 46% reduction in leakage power dissipation has been achieved while maintaining a 355-MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon. | |
| dc.format.extent | 130 bytes | - |
| dc.format.mimetype | text/html | - |
| dc.relation (關聯) | IEEE Journal of Solid-state Circuits, 41(8), 1707-1717 | |
| dc.title (題名) | A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor | |
| dc.type (資料類型) | article | en |
| dc.identifier.doi (DOI) | 10.1109/JSSC.2006.877248 | en_US |
| dc.doi.uri (DOI) | http://dx.doi.org/10.1109/JSSC.2006.877248 | en_US |
